The present invention relates to an information processing system for processing instructions using a pipeline processing scheme, or more in particular to a technique of assuring an accurate interruption in the case where a plurality of instructions are processed in pipeline.
The pipeline processing is a system in which the processing of instructions is divided into a plurality of processing stages having the same execution time (cycle), and a plurality of instructions are executed in overlapped fashion in each cycle pitch thereby to improve the processing speed. In realizing a pipeline processing system, a well-balanced design between the number of processing stages (number of pipeline stages) and the processing time per stage (machine cycle) is crucial for improving the processing speed of the information processing system.
Another important point for designing an information processing system of pipeline processing type is a processing scheme employed in the case where the pipeline is disturbed by such events as a failure in branching prediction or an interruption due to the occurrence of an exception.
The branching prediction is a scheme in which the instruction is executed in anticipation from a dynamically predicted jump address of a branching instruction to reduce the overhead of the branch instruction processing. The processing is continued when the prediction is successful. In the case where the prediction fails, however, the processing of the instruction stream for which the prediction has failed is required to be canceled and the instruction processing is required to be restarted immediately with a correct instruction stream. The dynamic frequency of occurrence of the branch instruction is generally as high as once per 3 to 5 instructions. An improved branch prediction accuracy and a reduced overhead time at the time of prediction failure are crucial for realizing a branch prediction system.
On the other hand, an interruption caused by various exceptions occurring during the execution of an instruction is generally not so frequent and requires analysis of the causes and countermeasures by software (interrupt handler, etc.) as well as interruption in hardware. A temporally critical processing, therefore, is not required as in the case of branching prediction failure. What is required in interruption is to meet the interrupt specification defined in architecture which is required to be observed by the information processing system.
In the case where an invalid instruction code interrupt occurs during the execution of a program, for example, the hardware does not process the instruction (suppression of the instruction) but notifies the program of the address of the occurrence of the interrupt and the probable cause thereof (invalid instruction code exception in this case) through an interrupt handler. Also in the case of a page fault interrupt, the hardware does not process the instruction (cancellation of the instruction) but the memory control software eliminates the cause of the page fault and restarts the processing from the time of occurrence of the interrupt, thus continuing to execute the program. In the case where an exception of fixed point overflow occurs, on the other hand, the instruction is processed (completion of the instruction) and the program is notified through the interrupt handler.
In the case of suppression or cancellation, the exception can be detected as soon as the instruction begins to be executed. In the case of completion, however, the exception cannot be detected before the instruction is executed. In an interrupt due to the occurrence of an exception, it is necessary to report the interrupt instruction address and the type of interrupt to the interrupt handler, etc. correctly and to assure the advisability of processing the interrupt instruction in accordance with the type of the interrupt.
FIGS. 1 to 3 show an example of the pipeline process for a conventional information processing system.
In FIGS. 1 to 3, reference characters IF designates an instruction read stage, D a decode stage, A an operand address calculation stage, B an operand read stage, L an operand transfer stage, E an execution stage, P an execution result transfer stage, and S an execution result storage stage for pipeline processing. In the time chart, EXCUTE designates an execution permit signal for permitting the execution of an instruction, WRITE a result storage permit signal for permitting the execution result to be stored in an operand buffer, SUPINT an exception detection signal generated upon detection of an exception of cancellation or suppression type, and CMPINT an exception detection signal generated upon detection of an exception of completion type.
FIG. 1 is a time chart showing the case of processing instructions continuously free of any cause disturbing the pipeline, or the case of what is called a normal execution, FIG. 2 the case in which an interrupt of suppression or cancellation type is generated in the instruction w, for example, and FIG. 3 the case in which an interrupt of completion type is generated in the instruction 2, for example.
Specifically, in the example of FIG. 2, an exception of cancellation or suppression type is detected in the instruction 2 and the exception detection signal SUPINT is generated in cycle C7, with the result that the generation of the result storage permit signal WRITE in the instruction 2 is suppressed in the next cycle C8. Consequently, the execution result of the instruction 2 is not stored in the operand buffer.
In the example of FIG. 3, an exception of completion type is detected in the instruction 2 and the exception detection signal CMPINT is generated in cycle C8, so that the generation of the result storage permit signal WRITE in the instruction 3 is suppressed in the next cycle C9. As a result, the execution result of the instruction 3 is not stored in the operand buffer.
As described above, according to the one-instruction processing mode for processing the instructions in pipeline one by one in the prior art, when an exception occurs, the signal for permitting the storage of the result of a particular instruction or a succeeding instruction is suppressed in accordance with the cause of the exception. In this way, an accurate interrupt required by the architecture is realized without executing an overrun instruction.
In the case where the timing from the detection of an exception to the writing of the result is critical, the process mentioned below is carried out, for example. Specifically, in the case where the storage of the result of an instruction execution overrun in a register is permitted, for example, the value on the register before updating the contents thereof is saved in a history buffer or the like. In the hardware interrupt processing, the value on the register invalidly updated by the overrun instruction is restored by writing back with the value saved in the history buffer, thus realizing a function equivalent to suppression. Also, a method is known in which a storage buffer is provided for the storage processing and the result storage stage is delayed to the timing capable of suppression by an exception.
The above-mentioned conventional techniques are described, for example, in "Superscalar Microprocessor Design", by Mike Johnson, Aug. 15, 1994, pp. 86-93, published by Nikkei BP Publication Center.
A method of further increasing the processing speed of the information processing system is by a superscalar processing system for pipeline processing of a plurality of instructions concurrently. For a precise interrupt to be realized in the conventional methods, a plurality of circuits are required for detecting, reporting and holding the interrupt information on an exception for a plurality of individual instructions processed concurrently or in parallel. Further, a complicate circuit is required to discriminate the instruction for completing the process and the instruction for suppression in accordance with which of the concurrently-processed instructions has generated an exception.